Power Integrity in Low-Power High-Speed Designs (DS364)

SynopsisWith the increasing demands for lower power consumption, higher signal speeds, decreasing feature sizes, denser designs and multi-function products, power and signal integrity effects have become the dominant factors limiting the performance of modern electronic products. These effects can be diverse, such as ground bounce, cross-talk, electromagnetic interference, etc., and can seriously impact the design performance at all hierarchical levels including integrated circuits, printed circuit boards, multi-chip modules, and backplanes.

A robust power network is essential for reliable operation of on-chip circuits. Voltage variations may lead to reduced noise margins and may increase propagation delays. Reduced noise margins can cause false switching of gates whereas increased delays may lead to timing errors and impede the overall operating speed of the chip. These issues coupled with high-frequency effects are making the modeling, analysis and design of power distribution networks (PDNs) consisting of chip, package and printed circuit boards, extremely challenging. If not considered during the design stage, power integrity effects can cause failed designs. Since extra iterations in the design cycle are costly, accurate prediction of these effects is a necessity in low-power high-speed designs.

On the other hand, today’s electrical engineers do not have sufficient training to tackle the multidisciplinary problem of signal integrity modeling, analysis, and design optimization. They are either trained in the basic analog area, digital aspects, or microwave areas only. However, the emergence of the signal integrity issues requires simultaneous understanding of inter-related issues from several different areas such as analog, digital, RF, thermal, and mechanical, since the traditional boundaries between these areas are fast vanishing.

This course provides a comprehensive and integrated approach for understanding the multidisciplinary problem of power integrity in high-speed designs.

What You Will Learn

• Power integrity issues in modern designs
• Basics of on-chip power grid
• Modules of power delivery network (PDN)
• Parameters of focus for PDN design: target impedance, noise margin
• Fundamentals of simultaneous switching noise
• Power integrity issues and EMI
• Sacred ground, return path, discontinuities
• Estimation of IR drop
• Modeling for power integrity
• Time-domain simulation methods for power integrity analysis
• Emerging parallel computing for large-scale power grids

Who Should Attend

• Low-power, high-speed designers
• Package engineers
• Digital, analog, or microwave engineers
• Product marketing engineers
• Application engineers
• Research, design and development engineers
• Test development engineers
• Product engineers
• System architects
• PCB layout specialists
• Measurement specialists
• EMC specialists
• Educators

PrerequisiteBasic knowledge and technical background in electrical engineering at diploma or degree levels.

Course MethodologyThis course is presented classroom style, with case studies to illustrate the concepts taught. The issues and concepts will be demonstrated through Matlab based experiments as well as through animations.

Course Duration2 days, 9am - 5pm

Course StructurePower Integrity: Fundamentals and PDN Modules

• Emerging area of power integrity - evolution and an integrated overview

Fundamental Concepts of Power Integrity (PI)

• Power integrity issues & their impact on modern designs
• Physical insight into power-integrity effects
• Fundamentals of transistor switching
• Basics of on-chip power grid
• Fundamentals of simultaneous switching noise
• PI issues and EMI

Modules of a Power Distribution Network

• The main components of a system PDN
• Fundamentals of transistor switching
• I/O signaling and voltage modes: Single-ended drivers and receivers; termination schemes used in single-ended systems; voltage-mode signaling; current-mode signaling; differential drivers and receivers; current flow, termination schemes; single-ended signaling versus differential signaling
• Voltage regulator modules
• Global/local decoupling capacitors
• Capacitor modeling and requirements

Overview of the Power Distribution Network and Noise Coupling Mechanisms

• Interconnect resistance, inductance, capacitance and conductance
• Types of high-speed signal, power paths: RC, RLC, RLGC, lossless, lossy, uniform, non-uniform
• Noise Coupling Mechanisms: resistive coupling; capacitive coupling; inductive coupling; common impedance coupling
• Vias

Case Studies & Simulation/Design Examples

Package, Inductance and Current Distribution Related Effects

• Package lead & interconnect inductance
• Package design, technology and Impacts for SSO
• PCB technology and board level PDN
• Sacred ground, return path, discontinuities
• Understanding simultaneous switching noise
• Current distribution related interconnect effects: skin, proximity & edge effects, frequency dependent parameters
• Ferrite beads and inductors

Modeling for Power Integrity at High Speeds

• Power integrity parameters of focus for PDN design: target impedance, noise margin
• Modeling of high-speed issues: delay, crosstalk, attenuation, reflections
• Time-frequency relations, frequency spectrum of digital signals

Modeling of Signal and Power Paths/Planes

• Modeling of interconnects: electrically short & long interconnects, lumped versus distributed
• Fundamentals of transmission line interconnects - Telegrapher’s equations
• Modeling of power planes
• Modeling of on-die PDN
• Estimation of IR drop

Power/Signal Integrity Challenges for Analog Simulators - An Overview

Modeling of Tabulated Data for Power Integrity Analysis

• Multiport parameters: S/Y/Z/T
• Concept and underlying theory of scattering parameters
• Rational function based macromodels: vector-fit, SPICE compatible realizations.
• Passivity verification and enforcement
• Delay extraction

Co-Modeling and Analysis of Power and Signal Integrity

Case Studies & Simulation Examples