Altera Quartus II Software Design Series: Foundation, Timing Analysis, Verification, and Optimization (PR179-33-0)

SynopsisYou will learn how to use the Quartus II software v. 8.0 to develop an FPGA or CPLD. You will create a new project, enter in new or existing design files, and compile your deisgn. You will also enter basic internal and I/O timing constraints & analyze a design for these timing constraints using TimeQuest, the timing analyzer in the Quartus II software. You will learn techniques to help you plan your design. You will employ Quartus II features that can help you achieve design goals faster. You will also learn how to plan & manage I/O assignments.

You will learn how to constrain & analyze a design for timing using the TimeQuest timing analyzer in the Quartus II software v. 8.0. This includes understanding FPGA timing parameters, writing Synopsys Design Constraint (SDC) files, generating various timing reports in the TimeQuest timing analyzer & applying this knowledge to an FPGA design. Besides learning the basic requirements to ensure that your design meets timing, you will see how the TimeQuest timing analyzer makes it easy to create timing constraints to help you meet those requirements.

You will learn features of the Quartus II software v. 8.0 & ModelSim software that will enable you to verify your FPGA design(1). You will learn how to simulate your design using the ModelSim-Altera simulator as well as understand what is required to simulate in other EDA simulation tools. You will learn how to use projects in the ModelSim-Altera tool & simulate Altera libraries. You will also estimate FPGA power consumption using tools found in the Quartus II software. You will use debugging tools available in the Quartus II software, such as the SignalTap II embedded logic analyzer & the Logic Analyzer Interface, & select the correct tool to effectively debug your design.

(1) Some (not all) features examined by this course apply to CPLD designs.

You will learn advanced features of the Quartus II design software v.8.0 that will enable you to shorten your design cycle as well as improve your design performance and utilization. You will use the incremental compilation flow and LogicLock regions in the Quartus II software to reduce compile times and preserve performance on selected regions of your designs. You will obtain your design goals in the area of performance, resource usage and power consumption by using design strategies, HDL coding styles and Quartus II software settings. You will also learn how to manage compile times effectively.

Course Highlight
DreamCatcher is a certified member of the Altera Training Partner Program (ATPP, http://www.altera.com/training), enabling us to provide engineers with high-quality training on Altera's products. We get regular information updates from Altera to ensure we have the tools to teach Altera's latest technologies. This course is collectively grouped from 4 teaching modules from ATPP:

• The Quartus II Software Design Series: Foundation (IDSW110)
• The Quartus II Software Design Series: Timing Analysis (IDSW120)
• The Quartus II Software Design Series: Verification (IDSW130)
• The Quartus II Software Design Series: Optimization (IDSW140)

What You Will Learn

• Make pre-project decisions to plan design
• Create, manage & compile Quartus II projects
• Plan & manage device I/O assignments using Pin Planner
• Assign clock & I/O constraints to improve design performance
• Analyze clock & input/output timing using TimeQuest
• Review compilation results
• Perform basic timing analysis with TimeQuest
• Create all required timing constraints (clock, I/O, multicycle, false paths) to fully constrain your FPGA design
• Write & manipulate SDC files for analysis & to control the compilation
• Apply timing constraints to the design to guide the Fitter to meet timing requirements
• Analyze timing with detailed TimeQuest reports
• Simulate a design using the ModelSim-Altera simulator
• Analyze power consumption with the PowerPlay power analyzer
• Debug designs in-system using the SignalTap II embedded logic analyzer
• Connect internal debug nodes to an external logic analyzer using the Logic Analyzer Interface
• View & edit embedded memory contents using the In-System Memory Content Editor
• Make incremental design changes with Chip Planner
• Define physical region constraints for an FPGA design using LogicLock regions
• Manage user-defined design partitions using the Quartus II incremental compilation flow
• Apply incremental compilation to the top-down & bottom-up design flows
• Use Quartus II software settings to improve internal & I/O timing, reduce logic resource usage & lower power consumption

Who Should AttendAsic-to-FPGA Designer, FPGA Designer, HardCopy Designer, High-Speed IO Designer

Prerequisite

• Attended DreamCatcher's course FPGA-based Digital System Design with HDL or
• Background in digital logic design
• Ability to describe a hardware system using VHDL, Verilog or EDA schematic tool
• Working knowledge of the Quartus II software

Course MethodologyThis course is presented in lecturing style, interspersed with hands-on sessions. Altera Quartus II and ModelSim Altera-Edition will be used extensively. Gaining hands on experience is emphasized.

Course Duration4 days, 9am - 5pm

Course StructureModule 1: Foundation (IDSW110) (1 day)
Introduction to Altera & devices
Quartus II feature overview
Design methodology
Projects

• Exercise 1

Design entry

• Exercise 2

Compilation

• Exercise 3

Settings & assignments

• Exercise 4

I/O Planning

• Exercise 5

Timing Analysis

• Exercise 6

Module 2: Timing Analysis (IDSW120) (1 day)
TimeQuest basics

• Exercise 1: Introduction to the TimeQuest tool

Timing analysis basics
TimeQuest reporting
Clock constraints

• Exercise 2: Clock constraints

I/O constraints

• Exercise 3: Synchronous I/O constraints

Constraining asynchronous signals
Timing exceptions

• False paths
• Multicycle constraints
• Exercise 4: Timing exceptions & analysis

Module 3: Verification (IDSW130) (1 day)
Basic simulation with ModelSim-Altera software

• Exercise 1: Basic simulation with ModelSim-Altera

NativeLink and Altera libraries with ModelSim-Altera software

• Exercise 2: Simulating with Altera Megafunctions

Power Analysis with PowerPlay

• Exercise 3: Power analysis

Quartus II debugging tools

• SignalProbe incremental routing
• In-System Sources and Probes
• SignalTap II embedded logic analyzer
• Exercise 4: Debugging with In-System Sources & Probes and SignalTap II
• Logic Analyzer Interface
• Chip Planner & Resource Property Editor

Module 4: Optimization (IDSW140) (1 day)
Quartus II software incremental compilation

• LogicLock regions
• Using incremental compilation
• Exercise 1: Quartus II incremental compilation

Optimization techniques

• Before optimization
• Quartus II optimization aides
• Timing optimization
• Exercise 2: Timing optimization
• Exercise 3: Timing optimization using PLLs
• Resource optimization
• Power optimization