Latch-Up - Physic, Circuit, Test and Characterization (SE105-35-0)

SynopsisLatch-up generally refers to the creation of a low-impedance path between power supply rails as a result of triggering a parasitic device in semiconductor devices. In this condition, excessive current flow is possible, and a potentially destructive situation exists due to electrical overstress (EOS). Latch-up may be caused by a number of triggering factors, including over-voltage spikes or transients, exceeding maximum ratings, and incorrect power sequencing. The best defense against latch-up is to adopt a good design practices with in-depth understanding of the latch-up mechanisms. No application can tolerate latch-up. Thus, it is necessary to be aware of its possibility, understand it, protect against it, and take measures to prevent it from happening.

Course Highlights
In this course, the fundamentals of latch-up to modern latch-up issues will be discussed. Comprehensive covering of latch-up include latchup physics and theory, device modeling, test structures, characterization, process and technology issues, and new latch-up issues in the industry today based on insight and research by the instructor.

What previous participants say about this course
Answers to the question 'what did you like most about the course'

•  "Instructor was able to explained based on latest trends and experience" - 2 Mar 07
•  "Course structure & coverage is comprehensive" - 2 Mar 07
•  "Voldman knows his stuff, yeah. Funny guy, not boring, lotsa stories/examples, good food. Lotsa breaks" - 2 Mar 07
•  "Good practical review" - 2 Mar 07
•  "Good presentation" - 2 Mar 07
•  "Process solutions section and the instructor expertise" - 2 Mar 07
•  "The explaination on the latch up issue in CMOS Circuit" - 2 Mar 07
•  "Well organised content" - 2 Mar 07

What You Will Learn

• Latchup Physics and Theory
• Latchup -C Classes of Latchup
• Latchup Test Structures
• Guard Ring Test Structures
• External Latchup Characterization
• Latchup Device Simulation
• Latchup Process Solutions
• Latchup Photoemission Characterization -C Optical Techniques
• Latchup Product Level Test Systems and Latchup Standards Specifications
• Latchup Computer Aided Design (CAD) Tools

Who Should AttendTechnicians, engineers, circuit designers, ESD engineers, and managers involved in design, testing or reliability of analog, RF or Mixed Signal Semiconductors / circuits including:

•  Design engineers
•  Process engineers
•  Test engineers
•  Yield analysis engineers
•  Product engineers
•  FA engineers
•  Reliability engineering
• Application engineering

PrerequisiteParticipants should have a basic background and understanding of semiconductor technologies, device physics and some circuit design basics. Previous familiarity will be advantageous in maximizing the impact of the course on the participant. Nonetheless, these concepts will be quickly reviewed as needed.

Course MethodologyThis course is presented in an interactive classroom style utilizing lecture, open discussion, and examples.

Course Duration1 day, 9am - 5pm

Course Structure1) Latchup Physics and Theory

• Latchup Circuit Schematics
• Overshoot
• Undershoot
• Latchup Initation Conditions: PNP Initiated Latchup, NPN Initiated Latchup
• Latchup Criterion - Beta Product Relationship: Generalized Tetrode Relationship, SAFE Region
• Latchup Propagation
• Latchup Domino Effect

2) Latchup - Classes of Latchup

• D.C. and Transient Latchup
• Internal Latchup and External Latchup
• Single Event Upset Initiated Latchup
• Power Supply Latchup
• Input Pin Latchup
• Pin-to-Pin
• Inter-circuit latchup
• Intra-circuit latchup
• ESD Power Clamp Initiated Latchup
• ESD Input Node Initiated Latchup

3) Latchup Test Structures

• PNPN Test Structure
• PNPN Test Structures with Guard Rings for Internal Latchup
• Triple Well PNPN Test Structures
• Deep Trench PNPN Test Structures for BiCMOS

4) Guard Ring Test Structures

• Guard Ring Structures for Internal Latchup
• Guard Ring Structures for External Latchup Characterization
• Injector-Collectr Structures
• Guard Ring Theory
• Guard Ring Efficiency Characterization
• Lateral Beta Evaluation

5) Latchup Characterization

• D.C Characterization Techniques: Well-Substrate Resistance Characterization Techniques-Transient latchup Characterization Techniques
• Automated Test Equipment

6) External Latchup Characterization

• Injector and Collector
• Relationship of Injection current and Circuit Robustness
• Latchup Propagation

7) Latchup Device Simulation

• P+/N+ Scaling
• STI Scaling
• Well Scaling

8) Latchup Process Solutions

• Heavily Doped Substrates
• Diffused N-Well
• Retrograde N-Wells
• P-Wells
• P+ Connecting Implants
• Shallow Trench Isolation
• Polysilicon Filled Deep Trench
• Biased Deep Trench
• Trench Isolation
• Heavily Doped Buried Layers (HDBL)
• Buried Grids (BG)

9) Latchup Photoemission Characterization - Optical Techniques

• Optical Techniques and Emission Microscope (EMMI) Tools
• Transmission Line Pulse - Pico-send Current Analysis (PICA) Tool and Animation

10) Latchup Product Level Test Systems and Latchup Standards Specifications

• Commercial Product Level Latchup Test Systems
• JEDEC Product Latchup Testing Specification

11) Latchup Computer Aided Design (CAD) Tools